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On the design of a function-specific reconfigurable: hardware accelerator for the MAC-layer in WLANs
ISBN
10.1145/968280.968352
Type
conference paper
Date Issued
2004-02-22
Author(s)
Pionteck, Thilo
Staake, Thorsten
Stiefmeier, Thomas
Kabulepa, Lukusa D.
Glesner, Manfred
Abstract
This work presents the hardware design of a dynamically reconfigurable function unit (RFU) to accelerate computation-intensive tasks in Medium Access Control (MAC) layers of WLANs. The function unit is integrated in a pipelined 32 bit RISC processor and provides full hardware support for the Advanced Encryption Standard (AES) as specified in upcoming WLAN standards such as IEEE 802.11i. Dynamic reconfiguration allows the processor to use arithmetic components and memory elements of the RFU not only for AES, but also for additional tasks common in the MAC-layer. With our approach it is possible to accelerate Reed-Solomon-Code generation, Cyclic Redundancy Checks as well as other encryption standards like SQUARE, Magenta and Twofish by supporting Galois Field multiplication and table look-ups. The integration of the reconfigurable unit in the processor core results in an architecture that can simultaneously support control-flow and data-flow oriented tasks. This architecture was prototyped onto a Virtex2 FPGA.
Language
English
HSG Classification
not classified
Refereed
Yes
Book title
Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Publisher
ACM
Publisher place
New York, NY, USA
Start page
258
End page
258
Event Title
Twelfth ACM International Symposium on Field-Programmable Gate-Arrays (FPGA 2004)
Event Location
Monterey, California
Event Date
22.-24.02.2004
Subject(s)
Division(s)
Eprints ID
3628